HW-V5-ML550-UNI-G【PDF 20/88 页】EVALUATION PLATFORM VIRTEX-5

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Chapter 3: Hardware Description

Clock Generation

The clock generation section of the ML550 Development Board provides all necessary

clocks for the Virtex-5 FPGA. Eight clock sources are provided:

R

?

?

?

?

?

?

Epson EG2121CA 2.5V 250-MHz differential LVPECL oscillator (Y4) for general use

Epson EG2121CA 2.5V 200-MHz differential LVPECL oscillator (Y3) for Virtex-5

FPGA ISERDES support

Epson EG2121CA 2.5V 133-MHz differential LVDS oscillator (Y2) for DDR memory

interface

Epson SG8002CA 3.3V 33-MHz LVCMOS single-ended oscillator (Y1) for SystemAce

device (U13)

Two differential SMA clock inputs (CLOCK-1: J3, J1 and CLOCK-2: J4, J2)

Two clock synthesizer ICS8442 devices (U18,U19)

The differential SMA clock inputs are connected to the global clock inputs of the FPGA. An

onboard 200-MHz oscillator calibrates the I/O delay, and an onboard 250-MHz oscillator is

provided for general use.

The two ICS8442 clock synthesizer devices output differential LVDS clocks in the

31.25 MHz to 700 MHz range.

The on-chip LVDS differential terminator is recommended for use in designs. The clock is

received by an IBUFGDS module, and beneath that module instantiation, the synthesis

attribute DIFF_TERM must be set to TRUE. Refer to the Virtex-5 FPGA User Guide ( UG190 )

for information and examples using SelectIO primitives for LVDS inputs.

Table 3-1 shows the clock generation components for the ML550 board.

Table 3-1:

Clock Generation – ML550 Rev 01 Board

Clock Source

Component

Reference Output

Designator Frequency

Output Type

Signal Name

FPGA Pin #

P N

Bank

Epson SG8002CA

Y1

33 MHz

3.3V LVCMOS

SYSACE_CLK

V33

N/A

13

Single-Ended

Epson EG2121CA

Y2

133 MHz

2.5V LVDS Differential

OSC_133M_P and N

R7

R8

12

Epson EG2121CA

Epson EG2121CA

Y3

Y4

200 MHz

250 MHz

2.5V LVPECL Differential OSC_200M_P and N

2.5V LVPECL Differential OSC_250M_P and N

L19

H17

K19

H18

3

3

ICS8442AY

ICS8442AY

SMA Connector

SMA Connector

SMA Connector

SMA Connector

U18

U19

J1

J2

J3

J4

31.25 MHz 3.3V LVDS Differential #1 LVDSCLKMOD1_P and N

to 700 MHz 3.3V LVDS Differential #2 CLKMOD1_FOUT1_P and N

31.25 MHz 3.3V LVDS Differential #1 LVDSCLKMOD2A_P and N

to 700 MHz 3.3V LVDS Differential #2 LVDSCLKMOD2B_P and N

SMA_CLK1_P

SMA_CLK1_N

SMA_CLK2_P

SMA_CLK2_N

AH18

J13

AB30

AK28

AF18

N/A

AD10

N/A

AG17

J14

AC30

AK27

N/A

AE18

N/A

AD11

4

N/A

17

21

4

4

22

22

20

ML550 Networking Interfaces Platform

UG202 (v1.4) April 18, 2008

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